CUPL Tutorial for EE 330

Architecture of the 22v10

The 22v10 device is a programmable logic device designed toimplement custom logic functions similar in complexity to the 74series of logic chips. It has the advantage of deliveringcustomized functions that might be difficult to implement or takemultiple chips using 74 series chips. Typical applications forthis are state machines used for things such as direct memoryaccess controllers in PCs.

The 22v10 consists of twelve inputs connected to a regularsum-of-products array and ten output logic macrocells. Thesum-of-products array has programmable interconnections thatdetermine the product terms connected to the or-gate. Efficientuse of these sum-of-products gates requires implementingfunctions in the same form and minimizing through the use ofmethods such as Karnaugh maps; there are a limited number ofinputs to these sum-of-products terms. The or-gates in each logicmacrocell are connected either to a D flip-flop in registeredform or directly to the output buffers in combinatorial form.Feedback is implemented through the connection of the D flip-flopoutput to a column in the product-term array. Other featuresinclude:

• A single product term to control the output buffer
• Every output has at least 8 product terms available
• A single product term is available to generate a global, asynchronous reset
• A single product term is available to generate a preset signal

for a full data sheet in PDF format on :

PALCE22V10